1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to SOI semiconductor devices comprising substrate diodes that are formed in the crystalline material of the substrate.
2. Description of the Related Art
The fabrication of integrated circuits requires a large number of circuit elements, such as transistors and the like, to be formed on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips, ASICs (application specific ICs) and the like, CMOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed above a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the distance between the source and drain regions, which is also referred to as channel length. Therefore, reducing the feature sizes and in particular the gate length of the field effect transistor has been an important design criterion.
In view of further enhancing performance of transistors, in addition to other advantages, the SOI (semiconductor- or silicon-on-insulator) architecture has continuously been gaining in importance for manufacturing MOS transistors due to their characteristics of a reduced parasitic capacitance of the PN junctions, thereby allowing higher switching speeds compared to bulk transistors. In SOI transistors, the semiconductor region, in which the drain and source regions, as well as the channel region, are located, also referred to as the body, is dielectrically encapsulated. This configuration provides significant advantages, but also gives rise to a plurality of issues. Contrary to the body of bulk devices, which is electrically connected to the substrate and, thus, applying a specified potential to the substrate maintains the bodies of bulk transistors at a specified potential, the body of SOI transistors is not connected to a specified reference potential, and, hence, the body's potential may usually float, due to accumulating minority charge carriers, unless appropriate countermeasures are taken.
A further issue in high performance devices, such as microprocessors and the like, is an efficient device internal temperature management, due to the significant heat generation of the transistors. Due to the reduced heat dissipation capability of SOI devices caused by the buried insulating layer, the corresponding sensing of the momentary temperature in SOI devices is of particular importance.
Typically, for thermal sensing applications, an appropriate diode structure may be used, wherein the characteristic of the diode may permit information to be obtained on the thermal conditions in the vicinity of the diode structure. The sensitivity and the accuracy of the respective measurement data obtained on the basis of the diode structure may significantly depend on the diode characteristic, i.e., on the diode's current/voltage characteristic, which may depend on temperature and other parameters. For thermal sensing applications, it may, therefore, typically be desirable to provide a substantially “ideal” diode characteristic in order to allow a precise estimation of the temperature conditions within the semiconductor device. In SOI devices, a corresponding diode structure, i.e., the respective PN junction, is frequently formed in the substrate material located below the buried insulating layer, above which is formed the “active” semiconductor layer used for forming therein the transistor elements. Thus, at least some additional process steps may be required, for instance, for etching through the semiconductor layer or a corresponding trench isolation area and through the buried insulating layer in order to expose the crystalline substrate material. On the other hand, the process flow for forming the substrate diode is typically designed so as to exhibit a high degree of compatibility with the process sequence for forming the actual circuit elements, such as the transistor structures.
For instance, typically, the PN junction of the substrate diode in the crystalline substrate material is formed on the basis of implantation processes, which are also applied in the device layer or active semiconductor layer for forming deep drain and source regions therein, in order to provide an efficient overall manufacturing flow. In this case, an opening, also referred to as a substrate window, is substantially formed so as to extend through the buried insulating layer and into the crystalline substrate material prior to performing the corresponding implantation process. Consequently, the dopant species is introduced into the crystalline substrate material, i.e., into the portion exposed by the substrate window, so that the PN junction is substantially aligned to the sidewalls of the substrate window, thereby providing a certain “overlap,” due to the nature of the implantation process and due to any subsequent anneal processes that are required for activating the dopant species in the drain and source regions of the transistors and to re-crystallize implantation-induced damage. Therefore, the characteristics of the PN junction of the substrate diode strongly depend on the characteristics of the PN junctions in the transistor elements, which, however, may not necessarily have a desired “ideal” diode characteristic. Furthermore, during the further processing, sophisticated metal silicide regions may be formed in the drain and source regions of the transistors, wherein these metal silicide regions are also formed in the doped areas of the substrate diode in the crystalline substrate material, wherein, however, due to device requirements for sophisticated transistors, highly conductive refractory metals, such as nickel, may frequently be applied, which may result in undue nickel diffusion. Consequently, the characteristics of the PN junction in the substrate diode may also depend on the characteristics of the metal silicide, wherein even nickel silicide protrusions may “bridge” the PN junction, thereby further deteriorating the overall performance of the substrate diode. Additionally, during the further processing, contact elements have to be formed so as to connect to the circuit elements in the device level and also to connect to the substrate diode, which may also result in certain irregularities and variabilities of the resulting diode behavior, as will be described in more detail with reference to FIGS. 1a-1f. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in an early manufacturing stage. As illustrated, the semiconductor device 100 comprises a substrate 101 comprising, at least in an upper portion thereof, a crystalline substrate material 102, such as a silicon material. Moreover, a buried insulating layer 103, for instance comprised of silicon dioxide, is provided above the crystalline substrate material 102 and, thus, vertically isolates a device layer 104 from the substrate material 102. The device layer 104 may initially represent a crystalline semiconductor material, such as a silicon material, and comprises, in the manufacturing stage shown, a plurality of “active” regions 104A, which are to be understood as semiconductor regions, in and above which circuit elements, such as transistors, have to be formed in a later manufacturing stage. Furthermore, the device layer 104 comprises one or more isolation structures 104K, which are typically provided in the form of shallow trench isolations in sophisticated semiconductor devices. For instance, the isolation structure 104K may be substantially comprised of silicon dioxide. Moreover, an implantation mask 105, such as a resist mask, is formed above the device layer 104 and comprises an opening 105A, which defines the lateral position and size of a “substrate window,” in which a substrate diode is to be formed in the crystalline substrate material 102.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following process strategy. The isolation structure 104K and any other isolation structures for laterally delineating the active regions, such as the active region 104A, in the device layer 104 are formed by providing trenches in the semiconductor layer 104 on the basis of sophisticated lithography and etch techniques, wherein any additional materials, such as hard mask materials and the like, are provided so as to obtain precise control of the lithography and etch process for forming the isolation trenches. Next, the trenches are filled with an appropriate insulating material, such as silicon dioxide, and any excess material thereof may be removed on the basis of chemical mechanical polishing (CMP), wherein a hard mask material, such as silicon nitride, may be used as an efficient stop layer. Next, the hard mask material may be removed by using wet chemical etch recipes and a plurality of implantation processes are typically performed based on appropriate masking regimes so as to establish the basic doping in the active regions 104A, for instance for N-channel transistors, P-channel transistors and the like. Prior to or after these “well implantations” for the active regions 104A, the implantation mask 105 is applied and a high energy implantation process 106 is performed so as to implant a well dopant species into the crystalline substrate material 102 through the layers 104 and 103, thereby forming a substrate well region 102W of a desired conductivity. For example, an N-type dopant species is used in order to form a PN junction with a P-type dopant species that is to be incorporated in a later manufacturing stage, when forming drain and source regions of P-channel transistors. It should be appreciated that a P-type dopant species may also be used to provide the substrate well region 102W, if desired. Thereafter, an anneal process is typically performed to activate the dopant species in the active region 104A and in the substrate well region 102W, thereby also reducing implantation-induced damage in the crystalline materials.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage, in which at least a part of a transistor 120 is formed in and above the active region 104A. The transistor 120 may comprise, in this manufacturing stage, a gate electrode structure 121, possibly in combination with a spacer element 122. Similarly, a “gate electrode structure” 121 is formed above the isolation structure 104K and has any appropriate lateral dimension so as to comply with the design requirements for forming contact elements and highly doped regions in the substrate well region 102W for providing a substrate diode. Moreover, an etch mask 107 is formed above the device layer 104 and comprises corresponding openings 107K, 107A, which, in combination with the structure 121, define the lateral size and position of openings to be formed so as to extend into the substrate well region 102W.
The semiconductor device 100 is typically formed in accordance with any appropriate manufacturing strategy for providing transistors in and above the active regions of the device layer 104, such as the transistor 120 formed in and above the active region 104A. For example, a gate dielectric material, in combination with an electrode material, such as polysilicon, metal-containing electrode materials and the like, are formed above the device layer 104 and are subsequently patterned by using sophisticated lithography and etch techniques. To this end, any further materials, such as dielectric cap materials, hard mask materials and the like, are typically provided in order to form the gate electrode structure 121 of the transistor 120 with the desired critical dimensions, which may be 50 nm and less in sophisticated semiconductor devices. At the same time, the structure 121 above the isolation structure 104K is provided, typically on the basis of less critical lateral dimensions, so that the structure 121 may in addition to the etch mask 107 act as a further etch mask in order to provide the corresponding openings to be formed in the isolation structure 104K and the buried insulating layer 103 with superior precision.
FIG. 1c schematically illustrates the semiconductor device 100 with a substrate window 108, which may be understood as the residue of the structure 121 in combination with the underlying portions of the isolation structure 104K and the buried insulation layer 103 in combination with corresponding openings 108K, 108A, which extend through the isolation structure 104K and the buried insulating layer 103 into the substrate well region 102W. The openings 108K, 108A may be formed on the basis of the etch mask 107 (FIG. 1b) by using appropriate plasma assisted etch recipes, for instance for etching through silicon dioxide material selectively with respect to resist material, silicon material and the like. After removing the etch mask, the further processing is continued by forming drain and source regions in the transistors in the device layer 104, thereby concurrently forming highly doped regions in the substrate well region 102W.
FIG. 1d schematically illustrates the semiconductor device 100 after any implantation processes for providing drain and source regions. As illustrated, the transistor 120, which, in the example shown, may represent a P-channel transistor, comprises highly doped drain and source regions 123, which may be formed on the basis of a further spacer structure 125, depending on the overall process strategy, i.e., depending on the requirements for profiling the lateral and vertical dopant profile in the transistor 120. It should be appreciated that, in any N-channel transistors (not shown), corresponding highly doped drain and source regions having an N-type conductivity are provided based on an appropriate masking regime. Similarly, a highly P-doped semiconductor region 124p is also provided in the substrate well region 102W. Consequently, in this case, the highly doped region 124p may represent an anode of a substrate diode 150 and may, thus, form a PN junction with the well region 102W. On the other hand, a highly N-doped region 124n is provided and may, thus, represent a cathode of the diode 150, wherein the highly doped region 124n may result in a desired reduced contact resistance of the substrate diode 150. Since the dopant species for the highly doped regions 124p, 124n of the substrate diode 150 have been incorporated via the openings 108A and 108K, respectively, the characteristics of the resulting PN junction are substantially determined by the implantation parameters and the characteristics of a subsequent anneal process, during which a certain degree of dopant diffusion may take place.
FIG. 1e schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, metal silicide, such as nickel silicide regions 125, are formed in the transistor 120, i.e., in the drain and source regions 123 and the gate electrode 121. Similarly, metal silicide regions 125 are formed in the highly doped regions 124p, 124n of the substrate diode 150, and possibly in the residue of the structure 121 of the substrate diode 150. The metal silicide regions 125 may be provided on the basis of any appropriate process strategy, i.e., depositing a refractory metal, such as nickel, and initiating metal diffusion, thereby forming the metal silicide. Thereafter, any non-reacted metal material, for instance formed on dielectric surface areas, is removed by efficient wet chemical etch techniques. It should be appreciated that, prior to the silicidation process, typically, appropriate cleaning recipes are applied, wherein a certain degree of material erosion in the regions 124p, 124n of the substrate diode 150 may occur. Consequently, upon forming the metal silicide 125 in these regions, a distance of the regions 125 with respect to the PN junction defined by the well region 120W and the highly doped region 124p may vary, thereby contributing to an increased variability of the resulting diode characteristics. Furthermore, a certain risk of creating nickel silicide protrusions may exist, in particular, if generally the implantation dose for forming the drain and source regions 123 may have to be reduced upon reducing the overall lateral dimensions of the transistor 120. Consequently, in particular at critical areas 102C, the characteristics of the PN junctions and, thus, of the substrate diode 150 as a whole may significantly depend on the specific process history.
FIG. 1f schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, an interlayer dielectric material 130 is formed above the device layer 104, thereby laterally embedding the transistor 120 and also passivating and enclosing the substrate diode 150. Frequently, the interlayer dielectric material 130 is provided in the form of two or more individual material layers, such as layers 131, 132, which are frequently comprised of silicon nitride and silicon dioxide, respectively. Furthermore, contact elements 133A, 133K are formed in the interlayer dielectric material 130 and connect to the substrate diode 150, while contact elements 134, 135 are provided so as to connect to the transistor 120, for instance to the drain and source regions 123 thereof and to the gate electrode structure 121 thereof.
The interlayer dielectric material 130 is typically formed by depositing the material 131, for instance, by plasma enhanced chemical vapor deposition (CVD) techniques so as to provide a silicon nitride material. Thereafter, the layer 132, for instance in the form of silicon dioxide, is deposited, for instance by sub-atmospheric CVD, high density plasma CVD and the like. Due to the presence of the substrate window 108, a pronounced surface topography may be created, even after planarizing the material 132 on the basis of well-established CMP techniques. Thereafter, an etch mask is formed on the basis of sophisticated lithography processes and the interlayer dielectric material 130 is patterned by applying plasma assisted etch recipes. During the corresponding etch process, very different etch depths in the substrate window 108 and for the device layer 104 have to be provided, thereby requiring superior etch stop capabilities of the silicon nitride material 125 in the transistor 120. Consequently, the silicon nitride material 125 is frequently formed according to process parameters which take into consideration, besides a moderately high resistance and a desired thermal stability, the etch stop characteristics required during the patterning of openings for the contact elements 133A, 133K. Consequently, these adaptations of material characteristics of the material 125 may also have an influence on the finally achieved characteristics of the substrate diode 150. Furthermore, the presence of the material 131 in the form of a silicon nitride material may also reduce the “ideality” of the substrate diode 150, wherein, however, the reason for this behavior is yet unknown. Consequently, upon forming the contact elements 133K, 133A and 134, 135, etch damage may be created in the transistor 120, while, on the other hand, performance of the substrate diode 150 may deteriorate, as discussed above.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.